CUSTOM GRAPHICAL SIMULATORS FOR VHDL LOGIC DESCRIPTIONS AND THE ALTERA NIOS II PROCESSOR

Embedded Sopc Design with Nios Ii Processor and Vhdl Examples

Montgomery Multiplication Coprocessor for Altera NIOS Embedded Processor

This paper describes scalable Montgomery Multiplication (MM) coprocessor optimized for Altera NIOS embedded processor implemented in reconfigurable hardware. Features of the NIOS soft processor Avalon Bus are used to connect the coprocessor as a memory mapped peripheral so that the overall performance is improved. Implemented coprocessor performs modular MM with large numbers (up to 4096 bits),...

Custom Fpga Cryptographic Blocks for Reconfigurable Embedded Nios Processor

This paper introduces two custom blocks for Nios reconfigurable embedded processor implemented on Altera Field Programmable Gate Arrays (FPGAs). When operations like modular multiplication and modular exponentiation of long integers or other complex algebraic functions are performed on a general-purpose processor they usually consume a lot of processor resources and execution times are not sati...

Nios II Processor Reference Handbook

Multimedia Decoder Using the Nios II Processor

Design Introduction Our design target was to build a low-cost, high-performance H.264 decoder with a prototype H.264 decoder created using multiple small FPGAs. H.264 is a computationally complex, advanced video standard for achieving high compression ratios. To cater to the needs of high throughput applications such as HDTV, which requires 216,000 macroblocks/second of throughput, designers us...